Intel Details 3D XPoint Memory, Future Products

At this year’s Intel Developer Forum, the company disclosed additional technical details about its forthcoming 3D XPoint memory, which has the potential to really change PC architecture by filling the gap between traditional main memory and storage.

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Intel and Micron, which together created the new memory and plan to produce it at a joint venture facility in Lehi, Utah, have said that 3D XPoint is 1,000 times faster than NAND flash and 10 times the density of DRAM. As such, it could be a faster alternative to today’s NAND flash memory, which has a lot of capacity and is relatively inexpensive, or work as a replacement or adjunct to traditional DRAM, which is faster but has limited capacity. At IDF, we got more details on how it might work in either of those solutions.   During the keynote, Rob Crooke, senior vice president and general manager of Intel’s Non-Volatile Memory Solutions Group, announced that Intel plans to sell data center and notebook SSDs as well as DIMMs based on the new memory in 2016 under the Optane brand name. He demonstrated an Optane SSD providing 5-7X the performance of Intel’s current fastest SSD running a variety of tasks.   Later on, he and Al Fazio, an Intel senior fellow and director of memory technology development, presented a lot of the technical details—though they are still keeping some important information under wraps, such as the actual material used for writing the data.  In that session, Crooke held up a wafer that he said contained the 3D XPoint memory, which will include 128 Gbits of storage per die. In total, they said the full wafer could hold 5 Terabytes of data.  Fazio said this concept is very scalable, in that you could add more layers or scale the manufacturing to smaller dimensions. The current 128 Gbit chips use two layers and are manufactured at 20nm. In a question-and-answer session, he noted that the technology for creating and connecting the layers is not the same as for 3D NAND and requires multiple layers of lithography, so costs may rise proportionally as you add layers after a certain point. But he said it was probably economical to create 4-layer or 8-layer chips, and Crooke joked that in three years, he’ll be saying 16 layers. He also said it was technically possible to create multi-level cells—such as the MLCs used in NAND flash—but it took a long time to do that with NAND and isn’t likely to happen soon because of manufacturing margins.   In general, Fazio said we could expect the memory capacity to increase on a cadence similar to NAND, doubling every couple of years, approaching Moore’s Law-style improvements.

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