IoT, Cost-per-Transistor Extend Lifetimes of Established Technology Nodes
Sourced through Scoop.it from: blogs.mentor.com
Mentor Graphics chiming in on something that those well informed souls understand about the high tech sector. Professionally speaking I detest the EDA tool suppliers, (very little value add for what they charge semiconductor firms for their tools and software) Mentor Graphics included. – However that being said they make the case for lower cost higher performing semiconductor process nodes in this article. “Established nodes are experiencing a much higher demand than one might normally expect at this point in their lifecycle. We believe this is driven by a couple of market dynamics, as discussed below. Their extended lives have brought some interesting physical verification, design-for-manufacturing (DFM), and manufacturing challenges to those seeking to leverage the benefits of these established nodes. Why are Established Nodes Experiencing a Long Life? The appetite for faster, smarter, lower-power, more interconnected, data-rich computing among the advanced economies worldwide (e.g. Europe, Japan, China, U.S., etc.) becomes more voracious by the day. Basic computing power continues to be driven by more powerful application processors, CPUs, GPUs, microcontrollers, memory, etc. marching down the Moore’s Law path. The iPhone, GoPro, and Nest have application processors and memory implemented at advanced nodes, such as 20 nm or 28 nm. However, much of the Internet of Things (IoT) functionality we crave, such as smart power management for longer battery life, and Wi-Fi and Bluetooth for more connectivity, are more cost-effective when implemented at established nodes between 40 nm and 180 nm. Consequently, the high consumer demand for these capabilities is driving demand for ICs manufactured using these processes. In a nutshell, the nodes that best support RF and mixed-signal IC designs with low power, low cost, and high reliability are experiencing much higher demand than in the past. The other dynamic benefiting the long life of established nodes—40/45 nm and 32/28 nm in particular—is the wafer cost trends at 20 nm and below. As I have previously written, with the semiconductor capital equipment industry stuck at the 193-nm wavelength, the only viable strategy to maintain a reasonable K1 and continue pursuing Moore’s Law is the use of multi-patterning. – Multi-patterning at 20 nm and below has enabled further scaling, but the inherent process complexity has driven up wafer cost, changing how fabless companies look at the jump to the next node. Just a few years ago, the jump would have been nearly automatic. However, with the cost structure of 20 nm and below, companies must seriously consider whether sales of the next design will really justify investing in the next node. We are seeing many companies make the jump to 20 nm, 16/14 nm, and 10 nm, but it tends to be those who are confident that they can sell in very high volumes while commanding premium average selling prices for their products. Also, the early adopters are companies that really need the advanced capabilities of the next node (e.g. high-end FPGAs, high-end application processors, CPUs, GPUs, memory, etc.) and feel they cannot be competitive at established nodes. However, more and more companies are finding that their business case doesn’t justify being an early adopter, and instead choose to stay at 28 nm and above.